Typically, a CMOS imager array includes a focal plane array of pixels, each one of the pixels including a photosensor, e.g., a photogate, photoconductor, or photodiode. The photosensor converts photons to electrons, which are typically transferred to a floating diffusion region connected to the gate of a source follower transistor. In addition to the photosensor, floating diffusion region, and source follower transistor, a pixel typically includes a charge transfer transistor for transferring charge from the photosensor to the floating diffusion region, a reset transistor for resetting the floating diffusion region to a predetermined charge level prior to photocharge transference, and a row select transistor for gating the output of the source follower transistor as a pixel output voltage.
CMOS imager circuits, processing steps thereof, and detailed descriptions of the functions of their various CMOS elements are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, U.S. Pat. No. 6,333,205, U.S. Pub. No. 2006/0256221, and U.S. Pub. No. 2006/0255381, each assigned to Micron Technology, Inc., and hereby incorporated by reference in their entirety.
FIGS. 1A-C respectively illustrate a top-down view layout (sometimes hereinafter referred “layout”), a cross-sectional view (taken along 1-1′ of FIG. 1A), and a circuit schematic of a four transistor (4T) CMOS pixel 100 employing a photodiode as the photosensor 101. When incident light 187 strikes the photosensor 101, electron/hole pairs are generated within the substrate in the vicinity of the p-n junction of the photodiode (represented at the boundary of n-accumulation region 122 and p+ surface layer 123). The photocharges (electrons) are collected in the n-type accumulation region 122 of the photosensor 101 during a charge integration period. After the integration period ends, the generated photocharges are transferred from the charge accumulation region 122 to the floating diffusion region 110 via a charge transfer transistor 106. The amount of charge at the floating diffusion region 110 drives the connected gate 108′ of the source follower transistor 108 to thereby produce a corresponding pixel output voltage VOUT, which is subsequently output on a column output line 111 via the row select transistor 109.
CMOS imager designs, such as that shown in FIGS. 1A-C for pixel 100, provide approximately a fifty percent fill factor, meaning only about half of the pixel 100 area is utilized in converting light to charge carriers. The remainder of the pixel 100 is allocated to the floating diffusion region 110, the charge transfer gate 106′ of the charge transfer transistor 106, as well as the source/drain regions 115 of the reset 107, source follower 108, and row select 109 transistors and their respective gates 107′-109′.
FIGS. 2A-B disclose a shared pixel component architecture which reduces the number of pixel components per each pixel to thereby increase the fill factor of each pixel, as well. As shown by the top-down view layout and circuit diagram of FIGS. 2A-B, two adjacent pixels 412-413 within a pixel group 450 each have respective photosensors 401A-B and charge transfer gates 406A′-B′ (as part of respective charge transfer transistors 406A-B), but the remaining pixel components 407-410 are shared between the adjacent pixels 412-413. These shared pixel components 407-410 are arranged as a shared trunk 490, which is located between two adjacent photosensors in a next pixel column.
The shared pixel components 407-410 include a common floating diffusion region 410, a reset transistor 407, a source follower transistor 408, a row select transistor 409 and their respective gates 407′-409′. The reset transistor 407 gates the supply voltage VAA-PIX to reset the floating diffusion node 410. The source follower transistor 408 receives the supply voltage VAA-PIX to generate the pixel output voltage VOUT based on the amount of charge stored by the floating diffusion node 410. The row select transistor 409 selectively reads out the pixel output voltage VOUT from the source follower transistor 408 to a column line 411.
Each pixel provides two signals as VOUT, a reset signal Vrst when the floating diffusion node is reset, and a photosignal Vsig when charge is transferred to the floating diffusion node 410 from a photosensor 401A-B. The floating diffusion node 410 is also driven to a reset potential, via the reset transistor 407, before photocharge transference. The potential of the reset floating diffusion node 410 is used to generate a corresponding pixel output voltage, which is sampled and held as a reset voltage Vrst by a sample and hold circuit 265 (FIG. 10). Thereafter, the amount of photocharge generated by the respective photosensor 401A-B is used to generate another corresponding pixel output voltage Vsig. The corresponding pixel output voltage VOUT is sampled and held as a signal voltage Vsig by the sample and hold circuit 265. A differential amplifier 267 subsequently generates a differential signal (Vsig−Vrst) from the photosignal Vsig and reset Vrst voltages. The differential signal (Vsig−Vrst), which indicates the pixel value of the pixel 412, compensates for common noise.
The pixels 412-413 alternate use of the shared pixel components 407-410. In particular, the pixels 412-413 are arranged on the same pixel column and operated in accordance with a rolling shutter, such as illustrated by FIG. 3. As shown, the rolling shutter utilizes at least two pointers, Reset and Read, which move down the pixel array 450 on a row-by-row basis. The Reset pointer resets and starts integration for all pixels of its presently designated row. The Read pointer subsequently reaches the same row and initiates signal readout of those pixels. A rolling shutter is one method of controlling the use of shared pixel components 407-410. Those of ordinary skill in the art will appreciate that other methods are available. They will also appreciate that the pixels 412-413 need not be arranged in the same column nor adjacent to one another in order to exercise such control.
The shared pixel component architecture of FIG. 2A, as well as other shared pixel component architectures, have some shortcomings. First, the layouts of the pixels 412-413 are not uniform because the respective charge transfer gates 406A′-B′, for example, have different locations (e.g., locations within their respective pixels 412-413) and different orientations (e.g., form different angles with a column-wise or row-wise direction of the pixels 412-413) to accommodate the grouped arrangement of the shared pixel components 407-410. In other words, the layouts of the pixels 412-413 are varied to direct their respective charge transfer gates 406A′-B′ toward the shared trunk 490. Such a lack of uniformity can increase the complexity of pixel array manufacture and decrease the consistency in pixel performance. Second, the number of pixels 412-413 cannot be increased or decreased without redesigning the layouts of the pixels 412-413 and their shared pixel components 407-410.